This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-064595, filed Mar. 11, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device, particularly, to an LSI with an improved wiring reliability.
The conventional RIE (reactive ion etching) wiring has characteristics as shown in FIG. 1. Specifically, a nonuniformity of defectiveness ("sgr" value of EM log-normal distribution) is large in a region of a certain wiring width. The reason for the presence of the particular region is that there is a region in which a bamboo ratio of a grain size to a width of the wiring is diminished. Specifically, the "sgr" value is large in a region where the bamboo ratio is about 10 to 50%. In a wiring EM (electro migration) endurance, an essential problem is derived from the presence of the particular region.
The conventional wiring structure includes a RIE wiring and a damascene wiring. In each of these wiring structures, all surfaces of the wiring layer made of Al, Cu, etc. are brought into contact with the insulating layer directly or with a liner interposed therebetween. Since such a surface has a high interfacial energy, the interfacial diffusion causes EM to proceed. As a result, the activation energy of EM is low, e.g., 0.2 to 0.6 eV. Also, during the EM testing, the metal atoms forming the wiring are migrated from the cathode (xe2x88x92) toward the anode (+). As a result of decreasing the density of the metal atoms on the side of the cathode, a tensile stress is generated on the side of the cathode.
If the tensile stress exceeds a critical stress, voids are generated in the wiring. If the insulating layer positioned to surround the wiring is capable of receiving the stress from the wiring and, thus, capable of being deformed elastically in accordance with the deformation of the wiring, EM-induced tensile stress is inhibited. However, it was customary in the past to use, for example, a plasma SiO2 film or a plasma SiN film as an interlayer, intra layer insulating film or a passivation film. What should be noted is that these plasma SiO2 film and plasma SiN film have large values of Young""s modulus exceeding 50 GPa. As a result, these films are scarcely deformed elastically upon receipt of the stress. It follows that the effect of inhibiting the tensile stress acting on the side of the cathode, said effect being produced by these films, is very small. Such being the situation, the conventional multi-layer wiring structure is low in EM reliability.
An object of the present invention is to provide a semiconductor device having a high EM reliability.
Another object is to provide a method of manufacturing a semiconductor device having a high EM reliability.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising:
a semiconductor substrate;
an insulating layer formed on the semiconductor substrate and having a groove portion for wiring; and
a wiring formed in the groove portion for wiring of the insulating layer,
wherein an inclined grain boundary is present in an optional cross section parallel to a longitudinal direction of the wiring; and
an inclination not more than 60xc2x0 is formed between the inclined grain boundary and a surface of the semiconductor substrate.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the semiconductor device comprises:
a semiconductor substrate;
an insulating layer formed on the semiconductor substrate and having a groove portion for wiring; and
a wiring formed in the groove portion for wiring of the insulating layer,
wherein an inclined grain boundary is present in an optional cross section parallel to a longitudinal direction of the wiring; and
an inclination not more than 60xc2x0 is formed between the inclined grain boundary and a surface of the semiconductor substrate,
the method comprising the steps of:
depositing a wiring material;
etching the deposited wiring material to form a groove; and
burying a wiring material in the groove.
According to a third aspect of the present invention, there is provided a semiconductor device, comprising:
a semiconductor substrate;
an insulating layer and a metallic wiring layer formed on the semiconductor substrate; and
an intermediate layer formed between the insulating layer and the metallic wiring layer in contact with both the insulating layer and the metallic wiring layer,
wherein the intermediate layer contains a metallic material constituting the metallic wiring layer, Si and O.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.